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by EE Times On Air
EE Times Current provides a deep dive into the most compelling stories in the electronics industry. Tune in to keep yourself current on what matters to design engineers and other tech industry professionals
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The most recent episodes — sign up to get AI-powered summaries of each one.
- 1 weeks ago42 min
Integrating Interface Memristors in the Back End of Line
IMChip’s founders say interface memristors are more reliable and scalable than filamentary ones. The Groningen spin-out grows the devices at high temperature, then transfers them onto silicon. In this month’s Brains and Machines, Sunny Bains talks with Tamalika Banerjee, chief scientific officer, and Ruben Hamming-Green, head of R&D, about their plan for an edge-AI prototype chip within two years. Giulia D’Angelo of the Czech Technical University in Prague and Ralph Etienne-Cummings of Johns Hopkins University join the discussion.
- 1 weeks ago
Integrating Interface Memristors in the Back End of Line
IMChip’s founders say interface memristors are more reliable and scalable than filamentary ones. The Groningen spin-out grows the devices at high temperature, then transfers them onto silicon. In this month’s Brains and Machines, Sunny Bains talks with Tamalika Banerjee, chief scientific officer, and Ruben Hamming-Green, head of R&D, about their plan for an edge-AI prototype chip within two years. Giulia D’Angelo of the Czech Technical University in Prague and Ralph Etienne-Cummings of Johns Hopkins University join the discussion.
- 3 weeks ago24 min
Beyond PPA: How Foundation IP Enables Predictable Execution and Lower TCO for AI-Era SoCs
As AI-driven SoCs move to advanced process nodes, design complexity, development cost, and execution risk are rising sharply. In this episode, Synopsys Executive Director of Product Management Ravi Todi explains why competitive power, performance, and area (PPA) are no longer sufficient on their own. Success in the AI era also depends on predictable execution and disciplined management of total cost of ownership (TCO) across the full SoC lifecycle.The discussion highlights how a holistic, silicon-proven Foundation IP platform—delivered as an integrated solution from a single trusted partner—can help reduce risk early, minimize integration issues and re-spins, accelerate yield ramp, and deliver differentiated PPA for high-performance compute AI, and edge AI designs. Ravi also explores how deep foundry alignment and EDA co-optimization reveal the true cost of fragmented IP sourcing beyond license price, enabling teams to meet demanding market requirements, achieve faster and more predictable tape-outs, and lower overall SoC TCO.
- Sep 18, 202657 min
Why Computing With Time Gives Neuromorphic AI an Edge
In this month's Brains and Machines, Dr. Ryad Benosman discusses event-based vision, retinal prosthetics, and neuromorphic startups with Dr. Sunny Bains of University College London. A co-founder of Prophesee, he explains why he believes AI's future must come from neuromorphic engineering. Discussion follows with Dr. Giulia D’Angelo from the Czech Technical University in Prague and Professor Ralph Etienne-Cummings of Johns Hopkins University.
- Sep 4, 202623 min
Where Software Meets Silicon: A Digital Twin Playbook
As systems become more software-defined, the traditional development model of waiting for hardware before serious software validation begins is no longer sustainable. Software teams need platforms earlier. Hardware teams need realistic workloads sooner. Verification teams need better ways to expose system-level issues before tapeout. We will look at how digital twins are becoming the shared foundation for this new HW/SW co-development model. Using virtual platforms, hardware emulation, and FPGA prototyping, teams can start earlier, collaborate more closely, and design/optimize/validate with greater confidence. We will also discuss new system-level verification challenges in power, performance, and DFT, showing how pre-silicon Hardware platforms can help teams find critical issues earlier and deliver more robust software-defined systems.
- Aug 26, 202624 min
Trust at Scale: The Next Challenge for AI-Driven Semiconductor Development
Artificial intelligence is accelerating semiconductor development, but more compute, more automation, and more engineering data do not automatically create better decisions. As design and manufacturing workflows become increasingly AI-enabled, a new constraint is emerging: trust. In this episode, Dr. Jim Shiely builds on themes from his Patterning the Singularity leadership work to explore the semiconductor industry’s “trust bottleneck” and why trustworthy engineering intelligence is becoming essential to future innovation.
- Aug 25, 20261h 0m
Do Spikes Need Common Language for Sensing and Learning?
On this month's episode of Brains and Machines, five engineers debate neuromorphic sensing and learning. Recorded at the Neuromorphic Hardware and Algorithms conference at the University of Sussex, the panel explores whether events and spikes are the right framework for integrating sensor modalities, motor control, and learning across systems. They also examine commercial directions and revisit the perennial question: what is neuromorphic engineering?The panelists are:Dr. Chiara Bartolozzi (Italian Institute of Technology) Dr. Federico Corradi (Eindhoven University of Technology) Dr. James Knight (University of Sussex) Dr. Laura Kriener (Institute of Neuroinformatics, Zurich) Dr. Sebastian Siegel (Peter Grünberg Institute, Jülich)The session is chaired by Dr. Sunny Bains (University College London), followed by a discussion with Dr. Giulia D’Angelo (Czech Technical University in Prague) and Professor Ralph Etienne-Cummings (Johns Hopkins University).
- Aug 21, 202618 min
Designing the AI Factory from the Rack Up
For years, AI infrastructure was measured at the scale of the data center. That's changed. In this episode, Neeraj Paliwal explains why the rack has become the indivisible unit of a modern AI system — designed as one system rather than a collection of servers — and why performance is no longer defined by the compute in any single box, but by how efficiently data moves, is stored, and is secured across the entire rack. And getting there depends on co-designing the silicon, memory, interconnect, and packaging together, with the IP foundation turning concentrated power into usable compute.
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About EE Times Current
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